ASTER Technologies’ TestWay

TestWay’s electrical Design for Test (DFT) analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate DFT in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.


Design for Test (DFT)

  • Electrical – automated rule checking for electrical DFT, at the design capture stage, to identify key areas of controllability at test and intelligently determine the access that is required
  • Physical – access and spacing is examined for interface and connection to UUT

This is key for any bed of nails testing like In-Circuit Test (ICT) and Functional.

Test Strategies

Engineering can perform test development inputs and predictive test coverage analysis for various test solutions including AOI, X-Ray, and ICT

Test Coverage Analysis

Actual coverage analysis from the different solutions to yield the true CCA overage